Integrated floating power transfer device with electromagnetic emission control circuit and method

ABSTRACT

An electromagnetic emission control circuit and method are provided for a power transfer device having a floating bus ( 214, 215 ) driven by a power and data system ( 107, 301, 310, 103 ). The electromagnetic emission control circuit includes one or more switch control circuits ( 402, 411 ) coupled between the floating bus and the power and data system for facilitating charging of the floating bus and for controlling electromagnetic emission from the power transfer device by constraining a slew rate on the floating bus. In one embodiment, the one or more switch control circuits include a first switch control circuit ( 402 ) electrically coupled to a high side bus node ( 214 ) of the floating bus and a second switch control circuit ( 411 ) electrically coupled to a low side bus node ( 215 ) of the floating bus. Transfer characteristics of the first and second switch control circuits are tailored to constrain the slew rate on the floating bus.

This application claims the benefit of U.S. Provisional No. 60/427,413,filed Nov. 18, 2002. This provisional application is hereby incorporatedby reference herein in its entirety.

The present invention relates in general to power transfer devices, andmore particularly, to a switch control circuit and method forconstraining electromagnetic emissions from an integrated floating powertransfer device.

Many system designs include power conversion circuitry to develop arequired operating voltage. One such power conversion circuit is knownas a charge pump. A charge pump is a device for creating increases insupply voltage or for inverting a supply voltage to generate a splitsupply. Many of these devices are related to applications usingnon-volatile memory circuits, which require a high voltage forprogramming. In a conventional charge pump power conversion circuit, theload device connects so that one terminal thereof is common to one ofthe supply terminals, typically the ground reference. U.S. Pat. No.4,807,104 discloses a power conversion circuit which is both a voltagemultiplying and inverting charge pump. However, the output of the powerconversion circuit remains referenced to the ground node.

In certain system implementations, it may be advantageous to power thesystem using a floating power transfer device. By floating the powertransfer device, if a terminal in the system were to short, then thesystem may still be able to continue to operate. For example, in anautomobile bus network, the signaling portion of the system on the buscould be floating relative to any other reference, such as ground orbattery positive This would provide enhanced fault tolerance by allowingcommunications to still occur notwithstanding a short at a terminalthereof.

The shortcomings of the prior art are overcome and additional advantagesare provided by the provision of a floating power transfer device whichincludes a floating bus, and a power and data system for driving thefloating bus. The power and data system include a charge pump circuit.Electromagnetic emission control is provided by at least one switchcontrol circuit coupled between the floating bus and the power and datasystem for facilitating charging of the floating bus and controllingelectromagnetic emissions from the floating bus by constraining a slewrate on the floating bus.

In another aspect, a circuit is provided which includes a first switchcontrol circuit for electrically coupling to a high side bus node of afloating bus, and a second switch control circuit for electricallycoupling to a low side bus node of the floating bus, wherein the firstswitch control circuit and the second switch control circuit comprisecomplementary control circuits for controlling charging of the floatingbus by a power and data system. A reference circuit is also provided forgenerating a first reference signal for the first switch control circuitand a second reference signal for the second switch control circuit. Thefirst reference signal and the second reference signal are employed bythe first switch control circuit and the second switch control circuit,respectively, for controlling electromagnetic emissions from thefloating bus by constraining a slew rate on the floating bus.

In a further aspect, a method for constraining electromagnetic emissionsfrom an integrated floating power transfer device is provided. Thismethod includes: tailoring a transfer characteristic of a first switchcontrol circuit to be electrically coupled to a high side bus node of afloating bus, and tailoring a transfer characteristic of a second switchcontrol circuit to be electrically coupled to a low side bus node of thefloating bus, wherein the first switch control circuit and the secondswitch control circuit comprise complementary control circuits forcontrolling charging of the floating bus by a power and data system; andgenerating, when in use, a first reference signal for the first switchcontrol circuit and a second reference signal for the second switchcontrol circuit, wherein the first reference signal and the secondreference signal are employed by the first switch control circuit andthe second switch control circuit, respectively, for controllingelectromagnetic emissions from the floating bus by constraining a slewrate on the floating bus.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention.

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 is a schematic of one embodiment of a conventionalvoltage-doubling charge pump circuit;

FIG. 2 is a schematic of one embodiment of a floating power transferdevice which enables the dual function of power and data transfer;

FIG. 3 is a schematic of one embodiment of an integrated circuitimplementation of a floating power transfer device;

FIG. 4 is a schematic of one embodiment of an integrated floating powertransfer device having switch control circuits for limitingelectromagnetic emissions, in accordance with an aspect of the presentinvention;

FIG. 5 is a graph of a transfer characteristic for a switch controlcircuit for the integrated floating power transfer device of FIG. 4, inaccordance with an aspect of the present invention;

FIG. 6 is a schematic of one embodiment of a switch control circuit forthe integrated floating power transfer device of FIG. 4, in accordancewith an aspect of the present invention;

FIG. 7 is a schematic of one embodiment of a N type transistor levelimplementation of the switch control circuit of FIG. 6, in accordancewith an aspect of the present invention;

FIG. 8 is a schematic of an enhanced N type transistor levelimplementation of the switch control circuit of FIG. 6, in accordancewith an aspect of the present invention;

FIG. 9 is a schematic of another enhanced N type transistor levelimplementation of the switch control circuit of FIG. 6, in accordancewith an aspect of the present invention; and

FIG. 10 is a schematic of one embodiment of a P type transistor levelimplementation of a switch control circuit such as shown in FIG. 7, inaccordance with an aspect of the present invention.

Reference is now made to the drawings, wherein the same referencenumbers used throughout different figures designate the same or similarcomponents. One embodiment of a power transfer device for powering aload 105 is shown in FIG. 1. This charge transfer device delivers chargeonto a capacitor CS 103 through switches SW4, SW3 101, 110 under controlof a signal generator 109. Charge is provided by a power supply voltage(V_DC) 107, one side of which is referenced to ground 108. A capacitorCH 104 provides the modified power supply for load 105. In this voltagedoubling example, capacitor 104 is charged with double the voltage ofcapacitor CS when switches SW1, SW2 102, 111 are closed by signalgenerator 106.

The power transfer device of FIG. 1 is referred to as a groundreferenced charge transfer device since the device supplies power to theload via a ground referenced capacitance. Circuits such as depicted inFIG. 1 are often used in applications such as E²ROM programming orextending the operating range of diverse analog circuits. As explainedfurther below, the present invention does not necessarily seek toincrease or invert an output voltage, but rather employs a similarswitching scheme to precharge a floating bus with a voltage that isclose to the original source-voltage. A circuit implemented inaccordance with an aspect to the present invention is designed to allowpower to be drawn continuously from the floating circuit, while asignaling scheme may partially or completely discharge the floating bus.The combined power and data feature of this apparatus has beenpreviously described in commonly assigned European patent document EP 1065 600 A2, the entirety of which is hereby incorporated herein byreference.

One embodiment of a floating power transfer device that enables the dualfunction of power and data transfer is shown in FIG. 2. A floating busis a bus that is electrically isolated from the ground reference 108 ofthe source voltage V_DC 107. In the circuit depicted in FIG. 2, theoutput VB+ 216 provides a continuous power source relative to thefloating bus, which is defined as the two nodes BUS+ 214 and BUS− 215.During the “data”phase when signal generator V_SW1 109 is at a logical1, the source switches SW3, SW4 110, 101 are “on” and the source voltageis driven onto the shuttle capacitor CS 103. The output switches SW1,SW2 102, 111 are “off” and the floating bus BUS+ 214 and BUS− 215 isavailable for signaling purposes. Power is available from the floatingbus due to the energy retained by the hold capacitor CH 204. A diode 212prevents the bus signal voltages from discharging the hold capacitor204. A “power” phase, when signal generator V_SW2 106 is at a logical 1,completes the two-phase cycle by turning on the bus switches 102, 111,while V_SW1 109 returns a logic zero, turning off the source switches101, 110. During this period, charge is delivered from the shuttlecapacitor 103 to the floating bus 214, 215, and consequently to the holdcapacitor 204. The voltage on the floating bus is restored to a valueclose to the source voltage. Depleted charge from the hold capacitor 204is restored, while maintaining the continuous source of power fromoutput VB+ 216, as required.

An integrated circuit (IC) implementation of a floating power transferdevice with a combined power and data feature is shown in FIG. 3. Inthis implementation, switches 101, 110 and 102, 111 are replaced by DMOStransistors 301, 310 and 302, 311, which are P type and N typetransistors. These devices require the addition of diodes 317, 318, 319,320 to maintain the isolation of the floating bus BUS+, BUS− 214, 215from the source voltage 107 and ground 108. This means that there areadditional electrical losses in this form of the circuit and theavailable output voltage relative to the original source voltage isreduced. The signal generators 106, 109, now require additionalcomplementary control sources 109b, 106b to drive the P-type DMOStransistor switches 301, 302 (with the N-type DMOS transistor switches310, 311 being driven by control sources 109, 106, respectively).Typically, the control sources are driven by digital signals, biased atthe prevailing logic-supply voltage, with the same phasing as describedabove in connection with the floating power transfer device of FIG. 2.

Power is again available in this implementation from the floatingcircuit due to energy retained by the hold capacitor CH 204. Diode 212again prevents the bus signal voltages from discharging the holdcapacitor 204. Output VB+ 216 at one side of load 205 provides acontinuous power source relative to the floating bus.

When a signal appears on the floating bus during the data phase, it maydrive the bus voltage to 0 V or some other predetermined intermediatevalue. For the remainder of this phase, the bus is held at that value.At the commencement of the power-phase, the bus transistor switches 302,311 turn on and the bus voltage is restored to the power level. In thissystem, the speed at which the bus voltage changes is dependent on theimpedance of the switches 302, 311 and diodes 318, 319 conductingcurrent from the shuttle capacitor CS 103 onto the floating bus. Whenthe rate of change is uncontrolled, as in this case, the edge of thevoltage waveform can be quite sharp. This results in a signal spectrumwith a high harmonic content. If the spectral content of the signalspreads into adjacent radio bands, then this is called electromagneticemission (EME). Certain applications of a floating power transfer devicesuch as depicted in FIG. 3 may require the system to limit the EME to aminimum. In one aspect, the present invention provides a technique forreducing/constraining the EME generated by the floating supply circuit.

Disclosed herein is a technique for constraining the EME output from afloating bus driven by a combined power and data system and based on anintegrated circuit (IC) charge pump circuit. As noted above, theuncontrolled slope of the power-phase voltage edge can generate EME thatinterferes with radio reception. Replacing the bus-switch transistors302, 311 of FIG. 3 with special switch control circuits as disclosedherein improves the EME performance of a target power transfer device.In one example, the transfer device is assumed to have two operatingmodes, a high-speed mode and a low-speed mode. It is possible to achievea better EME performance in the low-speed mode by taking advantage ofthe longer time interval available to deliver charge onto the bus. Thismeans that, in certain implementations, the switch control circuits havea selectable mode of operation that is dependent on the bus speed.

The floating bus forms a balanced system where the high-side BUS+ 214switch 302 and diode 318 are matched by a corresponding low-side BUS−215 switch 311 and diode 319, and which includes the implicit buscapacitance CBUS 213. The current flow is out of the BUS+ and into theBUS− terminal. Two complementary circuits are used to maintain thebalance of the system, while achieving the reduction in EME that isdesired. The circuit shown in FIG. 4 depicts one embodiment of afloating power transfer device with EME control.

In FIG. 4, the source-side switches 301, 310 and diodes 317, 320 remainas described in FIG. 3, while the BUS-side switches are replaced byswitch control circuits 402, 411 and a reference circuit 421. Switchcontrol circuit 402, in this example, is P-type transistor based andprovides a controlled current output, while switch control circuit 411,in this example, provides an N-type transistor controlled currentoutput. The reference circuit 421 provides two stable, temperaturecompensated reference signals that are used in setting operation of theswitch control circuits 402, 411.

The conceptual operation of the switch control circuits 402, 411 issimilar for both the “Pcontrol” 402 and the “Ncontrol” 411 circuits,with the N version being described in detail herein. The “Pcontrol”circuit 402 would comprise the complement of the N circuit. The“Ncontrol” circuit has a control input Ctrl and a reference Ref as wellas the switch nodes Vlo and Sw. When a logical 1 is applied to the Ctrlinput, the switch control circuit 411 is turned on, and with a logical0, it is off. When the voltage across the switch terminals Sw and Vlo islarger than a given threshold voltage (VswTh), the output current iskept at a constant value, dependent on the reference value.

A graphical view of one example of the voltage-current relation (i.e.,transfer characteristic) for the “on” switch is shown in FIG. 5 for adevice that limits the output current to, for example, 200 mA for switchvoltages greater than 1V.

In the circuit of FIG. 4, the negative switch voltage is not possiblebecause of the blocking diode D_1 319. At switch voltages less than 1Vthere is insufficient voltage to maintain the limit current and outputcurrent becomes a function of the switch voltage. When the switchvoltage is 0V, the current is also 0. As noted, reference block RefGen421 provides separate references for the two complementary switchcontrol circuits 402, 411. In the example of FIG. 4, a current is usedto provide the reference, but a voltage may also be used.

The HiLo input to the RefGen circuit 421 is used to select between twodifferent reference current levels that are determined by the bus speed.During high speed operation, the current is fixed at the maximum levelthat develops the necessary slew rate for the bus through the switchcontrol circuits 402, 411. With low speed operation, a period of lowcurrent is specified prior to the application of the maximum outputlevel. This creates a longer slew, and thus reduces the EME in the lowspeed mode.

To restate, switch control circuits 402, 411 are provided in thisexample to limit current to a fixed value so that with a rising voltageon the floating bus, the amount of electromagnetic emissions iscontrolled. The amount of EME depends upon the sharpness of the switchon and switch off characteristics of the switch control circuit. FIG. 5depicts one example of a desired transfer characteristic for theNcontrol 411 circuit of FIG. 4. The slope shown in FIG. 5 determines theeffective resistance of the switch. In the first phase, while thecurrent and voltage are rising, EME is generated, while in the secondphase the current remains substantially stable and is used to placecharge onto the hold capacitor 204 and bus capacitor CBUS 213. TheVswitch in FIG. 5 represents the voltage difference between Vlo and Swin Ncontrol circuit 411. As the voltage increases, the output currentalso increases until the Vsw equals approximately 1 volt, at which pointthe current becomes a constant 200 mA.

One embodiment of the N control circuit 411 is depicted in FIG. 6. Inthis embodiment, the function F(V_(ctrl), V_(Out)), controls the outputcurrent lout 601 based on the comparison between the reference voltageVRef resulting from the current generated by the source 609 flowingthrough resistance R1 604 to ground 603. Reference voltage VRefcomprises one input to an error amplifier 608, which has a second inputof VCmp, created by the output current flowing through resistor R0 605.The ratio between the resistor values R1 604 and R0 605 allows scalingbetween the output and reference currents. The control operator 606ensures that the output current remains essentially constant as theoutput voltage changes. As VOut approaches the same values as VCmp, theoutput regulation is unable to maintain the full output current and thecurrent reduces. Switch 610 turns off the output current lout 601 whenthe switch is “on”, under the control of signal Vsw 611. Resistor R2 612allows the control VCtrl to be pulled to 0V to ensure that the output isfully disabled.

FIG. 7 depicts one transistor level implementation of an “Ncontrol”circuit such as described above in connection with FIG. 6.

With this design, the output is partitioned into two branches controlledby DMOS switches MND1 717 for BranchA and MDN0 716 for BranchB.Splitting the output current into two paths allows a smallseries-resistance RBA 714 in BranchA to create a sense voltage to becompared to the generated reference voltage, without introducingadditional resistance into the main current path, BranchB.

The input node Iref 722 supplies the reference current I_(R) that isfolded through current mirrors J_4, J_3, J_5 721, 712, 711. The mirrorsJ_2, J_1, J_0 708, 706, 705 fold the reference current from the positivesupply. Mirror J_0 705 doubles the output current to 2·I_(R) andprovides the correct biasing current I_(R), for diode-connected NMOStransistor M2 720 and the remaining current (also I_(R)) is used tocreate an offset voltage across resistor RIB 718. An identical currentI_(R), biases the two NMOS transistors M3 703 and M2 720. Device M3 703provides the gain of the circuit. The voltage Io·RBA is compared to thereference voltage obtained from I_(R)·RIB, the additional resistor RIA719 corrects for the small error introduced by the addition of thereference current I_(R) to the output current in BranchA. With thecurrent I_(R) in each path, the values of resistors R0, RIA and RIB areidentical. The final value of the output current Iout 701 through theblocking diode D_2 702 is obtained from the following:${Io} = \frac{{IR} \cdot {RIB}}{RBA}$ Iout = Io ⋅ (N + 1)

The offset at the source of transistor MND1, created by the currentthrough RBA 714, is compensated at the gate drive nodes GateBA andGateBB by the resistor RO 704. When the circuit is operating inequilibrium the current through RO 704 is the same as the current in RIB718, and both devices have the same voltage. The feedback loop around RO704, MND1 717, RBA 714, M2 720, RIB 718 and M3 703 ensures that thevoltage across RO 704 is the same as that across RBA 714. This conditionremains true while the output voltage on the drain node remainssufficient to keep both DMOS switches MND1 717 and MND0 716 insaturation. In dynamic conditions, such as the pull-down of the outputon node Iout, and consequently on the drain, an amount of charge is lostto the gate of MND1 717 that creates an error in the voltage drop acrossR0 714. Similarly, an additional error is introduced by the current lostin charging the gate of MND0 716 that alters the bias condition of NMOStransistor M3 703. If the gate charging current is small relative to thebias current then the accuracy of the output current (N+1)·Io issufficient for the purposes of this apparatus.

The switching of the output node is achieved by a control signal Vsw 710that drives the gate switches SW_0 713 and SW_1 715. When the switchesare turned on, the two gate nodes GateBA and GateBB are pulled down toground, turning off both of the output DMOS transistors, MND1 717 andMND0 716, The current loss through the switches is limited by thecurrent mirror J_1 706 to be I_(R).

Errors introduced by the output Iout 701 slewing mentioned in connectionwith FIG. 7, can be addressed by the circuit shown in FIG. 8. Two scaledclass-B amplifiers 825, 826 are used to buffer a replication of theoriginal amplifier output-stage. This is formed by the addition NMOStransistor N_9 824, resistor ROX 823 and current mirror J_6 827. The N:1scaling at the output devices (MND1 817, MND0 816) requires a similarscaling in the gate current. This is achieved by scaling the buffers,with the buffer 825 driving GateBB being N times the strength of thebuffer 826 that drives node GateBA. When the circuit turns on, theoutput lout begins to fall inducing current in the gate nodes due to theparasitic gate-capacitance on the output DMOS devices. When thishappens, the buffers turn on and supply the additional current into thegate nodes. As equilibrium is achieved, the buffer stops supplying theadditional current.

Returning to FIG. 7, when the output is disabled, the amplifier limits,with its gain transistor M3 703 driven into an off state. The switches713, 715 sink the bias current I_(R) that is also lost through the otherstages. An additional variation of the circuit of FIG. 7 is depicted inFIG. 9. FIG. 9 provides an improvement in the switching time fromcontrol input to control output. To reduce the power losses in thecircuit, a variation in the circuit splits the bias current sources intotwo parts for each branch. One part remains static, while the secondpart is switched. A separate control signal 924, two additional switches925 and 926, with mirror devices 927 and 923 are combined to form theenhancements to the basic switch control circuit of FIG. 7. Keeping thecircuit partly biased ensures that the startup of the circuit isimproved. The overall current ratios are maintained so that when thecircuit is on, the circuit behaves identically to that of FIG. 7.

The enhancements of FIG. 8 and FIG. 9 may also be combined into a singleswitch control circuit to obtain both the described improvements. In afull circuit implementation, the current mirrors may require cascodingto increase their output impedance. The use of cascode devices dependson the accuracy required for the output current Iout.

One embodiment of the complementary “Pcontrol” circuit is depicted inFIG. 10. FIG. 10 is essentially a PMOS/PDMOS version of the circuit ofFIG. 7. Mirrors that were connected to ground in FIG. 7 now connect tothe positive supply, and vice-versa for the remaining mirrors. P-typedevices replace any N-type devices, and the operation of the circuitremains the same.

Although preferred embodiments have been depicted and described indetail herein, it will be apparent to those skilled in the relevant artthat various modifications, additions, substitutions and the like can bemade without departing from the spirit of the invention and these aretherefore considered to be within the scope of the invention as definedin the following claims.

1. A device comprising: a floating bus; power and data system fordriving the floating bus, the power and data system comprising a chargepump circuit; and at least one switch control circuit coupled to thefloating bus and the power and data system for facilitating charging ofthe floating bus and for controlling electromagnetic emission from thedevice.
 2. The device of claim 1, wherein the at least one switchcontrol circuit comprises a first switch control circuit and a secondswitch control circuit, the first switch control circuit comprising atleast one P type transistor circuit, and the second switch controlcircuit comprising at least one N type transistor circuit and whereinthe first switch control circuit and the second switch control circuitcomprise complementary circuits.
 3. The device of claim 2, wherein thefirst switch control circuit is electrically connected to a first busnode of the floating bus and the second switch control circuit iselectrically connected to a second bus node of the floating bus.
 4. Thedevice of claim 1, wherein the charge pump circuit comprises anintegrated circuit employing at least one transistor and diode pair. 5.The device of claim 1, wherein the at least one switch control circuitis operable in at least a low speed mode and a high speed mode, withmode of the at least one switch control circuit being dependent upon adesired floating bus charging speed.
 6. The device of claim 1, whereinthe floating bus comprises a balanced bus system having a high side busnode and a low side bus node, and wherein the at least one switchcontrol circuit comprises a first switch control circuit and a firstdiode connected to the high side bus node and a second switch controlcircuit and a second diode connected to the low side bus node.
 7. Thedevice of claim 6, wherein the first switch control circuit and thesecond switch control circuit are driven by a reference circuit, thereference circuit generating a first reference signal for the firstswitch control circuit and a second reference signal for the secondswitch control circuit.
 8. The device of claim 7, wherein-when a voltageacross a first terminal and a second terminal of the first switchcontrol circuit is greater than a threshold value, output current fromthe first switch control circuit is constant at a value dependent on thefirst reference signal, and when voltage across a first terminal and asecond terminal of the second switch control circuit is greater than thethreshold value, output from the second switch control circuit isconstant at a value dependent on the second reference signal.
 9. Thedevice of claim 1, wherein the at least one switch control circuitcontrols electromagnetic emission from the device by constraining theslew rate on the floating bus.
 10. A circuit comprising: a first switchcontrol circuit for electrical coupling to a high side bus node of afloating bus, and a second switch control circuit for electricalcoupling to a low side bus node of the floating bus, wherein the firstswitch control circuit and the second control circuit comprisecomplementary circuits for controlling charging of the floating bus by apower and data system; and a reference circuit for generating a firstreference signal for the first switch control circuit and a secondreference signal for the second switch control circuit, wherein thefirst reference signal and the second reference signal are employed bythe first switch control circuit and the second switch control circuit,respectively, for controlling electromagnetic emissions from thefloating bus by constraining a slew rate on the floating bus.
 11. Thecircuit of claim 10, wherein the power and data system comprises acharge pump circuit, the charge pump circuit comprising an integratedcircuit.
 12. The circuit of claim 10, wherein the first switch controlcircuit comprises a P type transistor circuit, and the second switchcontrol circuit comprises a complementary N type transistor circuit. 13.The circuit of claim 10, wherein the first switch control circuit andthe second switch control circuit are each operable in at least a lowspeed mode and a high speed mode, with mode of the first switch controlcircuit and the second switch control circuit being determined by thefirst reference signal and the second reference signal generated by thereference circuit in response to an input control signal which isdependent upon a desired floating bus charging speed.
 14. A methodcomprising: tailoring a transfer characteristic of a first switchcontrol circuit to be electrically coupled to a high side bus node of afloating bus, and tailoring a transfer characteristic of a second switchcontrol circuit to be electrically coupled to a low side bus node of thefloating bus, wherein the first switch control circuit and the secondswitch control circuit comprise complementary control circuits forcontrolling charging of the floating bus by a power and data system; andgenerating, when in use, a first reference signal (PRef) for the firstswitch control circuit and a second reference signal (NRef) for thesecond switch control circuit, wherein the first reference signal andthe second reference signal are employed by the first switch controlcircuit and the second switch control circuit, respectively, forcontrolling electromagnetic emission from the floating bus byconstraining a slew rate on the floating bus.
 15. The method of claim14, wherein the power and data system comprises a charge pump circuit,the charge pump circuit comprising an integrated circuit.
 16. The methodof claim 15, further comprising integrating the first switch controlcircuit and the second switch control circuit on the integrated circuitwith the charge pump circuit.
 17. The method of claim 14, wherein thefirst switch control circuit and the second switch control circuit areeach operable in at least a low speed mode and a high speed mode, withmode of the first switch control circuit and second switch controlcircuit being determined by the first reference signal and the secondreference signal, wherein the first reference signal and the secondreference signal are generated by a reference circuit electricallycoupled to the first switch control circuit and the second switchcontrol circuit, and wherein the method further comprises providing aninput control signal to the reference generator for controlling a valueof the first reference signal and a value of the second referencesignal.
 18. A circuit comprising: means for tailoring a transfercharacteristic of a first switch control circuit to be electricallycoupled to a high side bus node of a floating bus, and for tailoring atransfer characteristic of a second switch control circuit to beelectrically coupled to a low side bus node of the floating bus, whereinthe first switch control circuit and the second switch control circuitcomprise complementary control circuits for controlling charging of thefloating bus by a power and data system; and means for generating, whenin use, a first reference signal (PRef) for the first switch controlcircuit and a second reference signal (NRef) for the second switchcontrol circuit, wherein the first reference signal and the secondreference signal are employed by the first switch control circuit andthe second switch control circuit, respectively, for controllingelectromagnetic emission from the floating bus by constraining a slewrate on the floating bus.